At Ablee, we believe that people are our most valuable asset. We are committed to a culture of respect and development, fostering a humane and supportive work environment. We empower our team members to be professional, expert, dedicated, and joyful in their work.
We build a strong community of shared interests and purpose with every employee, working together to build careers, achieve growth, and create a win-win future.
Senior Physical Design Engineer
3
Shenzhen
2025.02.01
Description:
1. Master and oversee the design implementation process for advanced processes, participating in chip design from RTL to GDSII.
2. Responsible for chip planning and layout, dividing the top-level design into lower-level modules.
3. Power and clock distribution and planning.
4. Layout and routing, including all aspects from top-level design to lower-level modules.
5. Static timing, power, noise, and manufacturability optimization and analysis.
Qualifications:
1. Bachelor's degree or higher with over 3 years of experience in chip backend design.
2. Proficient in using PR tool Innovus with experience in the entire backend flow from NETLIST to GDSII.
3. Proficient scripting skills using languages such as Tcl, Perl, Python, etc.
4. Prior experience in high-speed interface design, such as LVDS, MIPI, is a plus.
5. Excellent communication and teamwork skills. 6. Fluent in English for reading and writing.
Submit Your Resume
Senior Physical Design Engineer
3
Shenzhen
2025.02.01
Description:
1. Master and oversee the design implementation process for advanced processes, participating in chip design from RTL to GDSII.
2. Responsible for chip planning and layout, dividing the top-level design into lower-level modules.
3. Power and clock distribution and planning.
4. Layout and routing, including all aspects from top-level design to lower-level modules.
5. Static timing, power, noise, and manufacturability optimization and analysis.
Qualifications:
1. Bachelor's degree or higher with over 3 years of experience in chip backend design.
2. Proficient in using PR tool Innovus with experience in the entire backend flow from NETLIST to GDSII.
3. Proficient scripting skills using languages such as Tcl, Perl, Python, etc.
4. Prior experience in high-speed interface design, such as LVDS, MIPI, is a plus.
5. Excellent communication and teamwork skills. 6. Fluent in English for reading and writing.
Submit Your ResumeSenior Physical Design Engineer
3
Shenzhen
2025.02.01
Description:
1. Master and oversee the design implementation process for advanced processes, participating in chip design from RTL to GDSII.
2. Responsible for chip planning and layout, dividing the top-level design into lower-level modules.
3. Power and clock distribution and planning.
4. Layout and routing, including all aspects from top-level design to lower-level modules.
5. Static timing, power, noise, and manufacturability optimization and analysis.
Qualifications:
1. Bachelor's degree or higher with over 3 years of experience in chip backend design.
2. Proficient in using PR tool Innovus with experience in the entire backend flow from NETLIST to GDSII.
3. Proficient scripting skills using languages such as Tcl, Perl, Python, etc.
4. Prior experience in high-speed interface design, such as LVDS, MIPI, is a plus.
5. Excellent communication and teamwork skills. 6. Fluent in English for reading and writing.
Submit Your Resume
Office: Room 1309, No.21 Wanjun Building, Baoxing Rd, Bao'an Center, Shenzhen, Guangdong 518000, China.
Factory address: BLDG 8, Xufa Industrial, Tongfuyu Zone, Shangcun, Gongming, Guangming District, Shenzhen, China.
sales@ablee.com.cn sales@megaudio.cn
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